Pulse current generation circuit

ABSTRACT

An N-transistor switches a current of a first constant current source by a positive input pulse to generate an output pulse current where an overshoot and an undershoot appear. A P-transistor switches a current of a second constant current source by a negative correction pulse applied at timing of occurrence of the overshoot to generate a correction pulse current. Another N-transistor switches a current of a third constant current source by a positive correction pulse applied at timing of occurrence of the undershoot to generate a correction pulse current. These correction pulse currents are added to the output pulse current to obtain a current as a wavelength where the overshoot and undershoot are largely reduced.

BACKGROUND OF THE INVENTION

[0001] 1) Field of the Invention

[0002] The present invention relates to a technology for generating ahigh-frequency pulse current in order to drive a laser diode or thelike.

[0003] 2) Description of the Related Art

[0004]FIG. 19 is a circuit diagram that shows a configuration example ofa conventional pulse current generation circuit formed of an integratedcircuit with MOS transistors. However, a configuration example ofbipolar transistors is not shown.

[0005] As shown in FIG. 19, this pulse current generation circuitincludes NMOS transistors 101 and 102, and a bias voltage source 103. Alaser diode 106 is connected to an IC output terminal 104 and anexternal power supply 105. A snubber circuit 107 is connected inparallel with the laser diode (LD) 106.

[0006] A bias voltage of a positive polarity is input from the biasvoltage source 103 to the NMOS transistor 101 at its gate electrode. TheNMOS transistor 101 is connected at its drain electrode to the IC outputterminal 104 and connected at its source electrode to the NMOStransistor 102 at its drain electrode. The NMOS transistor 102 isconnected at its source electrode to ground (GND). An input pulse phaving a predetermined pulse width is applied to the NMOS transistor 102at its gate electrode.

[0007] In the configuration heretofore explained, the bias voltage ofthe positive polarity is applied from the bias voltage source 103 to thegate electrode of the NMOS transistor 101. Thus, the NMOS transistor 101is in the ON state, and forms a constant current source that flows apreset constant current. When the input pulse p is applied to the gateelectrode of the NMOS transistor 102 and the NMOS transistor 102 turnsON, the LCD 106 is connected at its cathode to ground (GND) via the NMOStransistors 101 and 102.

[0008] Accordingly, the LD 106 turns ON. A pulse current having a pulsewidth equivalent to that of the input pulse p flows to the ground (GND)via the LD 106 and the NMOS transistors 101 and 102. In other words,when the NMOS transistor 102 is turned ON by the input pulse p, anoutput pulse current having the pulse width is applied to the LD 106,and consequently the LD 106 is subjected to pulse driving.

[0009] If the slew rate becomes high in pulse light emission of the LD106, then overshoots, undershoots, and ringings occur due to parasiticinductance components of an IC substrate. In the worst instance, the LD106 is destroyed.

[0010] In the conventional art, therefore, there is adopted a method ofconnecting the snubber circuit 107, which is a filter made up of aseries circuit consisting of a resistor and a capacitor, in parallelwith the LD 106 as shown in FIG. 19 in order to reduce the overshoots,undershoots, and ringings.

[0011] In the method of externally providing the snubber circuit 107 inorder to reduce the overshoots, undershoots, and ringings, however, thenumber of components increases and requires much labor to set constantsof the snubber circuit 107. Due to addition of the snubber circuit 107,the slew rate is lowered. This results in a problem that the datatransfer rate cannot be increased in application to communication orstorage.

[0012] On the other hand, when a distributed parameter circuit can besupposed as in long external wiring, there is a method of effectingimpedance matching and thereby reducing overshoots, undershoots, andringings caused by reflection.

[0013] This method is used frequently when wiring impedance is not sohigh and a pulse voltage is output with low output impedance. It isdifficult to effect matching in an IC because it is necessary to makethe impedance of external wiring a certain constant value. In otherwords, the pulse generation type is comparatively high in outputimpedance, and consequently the impedance matching technique cannot beadopted.

SUMMARY OF THE INVENTION

[0014] It is an object of the present invention to provide a pulsecurrent generation circuit that obviates the need of a componentprovided outside, that can improve overshoots and undershoots owing toprocessing conducted within an IC, and that can generate a pulse currenthaving a high slew rate.

[0015] The pulse current generation circuit according to one aspect ofthis invention, includes a first N-type transistor that is connected ata first signal electrode thereof to an output terminal of an outputpulse current and that functions as a first constant current sourceaccording to a bias voltage of a positive polarity, and a second N-typetransistor that is connected to a second signal electrode of the firstN-type transistor and ground and that switches a current of the firstconstant current source in response to an input pulse of a positivepolarity and thus generates the output pulse current. The circuit alsoincludes a first P-type transistor that is connected at a first signalelectrode thereof to the output terminal and that functions as a secondconstant current source according to a bias voltage of a negativepolarity, and a second P-type transistor that is connected to a secondsignal electrode of the first P-type transistor and a power supply andthat switches a current of the second constant current source inresponse to a first correction pulse of a negative polarity appliedthereto at timing of occurrence of an overshoot in the output pulsecurrent and thus generates a first correction pulse current. The circuitfurther includes a third N-type transistor that is connected at a firstsignal electrode thereof to the output terminal and that functions as athird constant current source according to a bias voltage of a positivepolarity, and a fourth N-type transistor that is connected to a secondsignal electrode of the third N-type transistor and the ground and thatswitches a current of the third constant current source in response to asecond correction pulse of a positive polarity applied thereto at timingof occurrence of an undershoot in the output pulse current and thusgenerates a second correction pulse current.

[0016] The pulse current generation circuit according to another aspectof this invention, includes a first N-type transistor that is connectedat a first signal electrode thereof to an output terminal of an outputpulse current and that functions as a first constant current sourceaccording to a bias voltage of a positive polarity, and a second N-typetransistor that is connected to a second signal electrode of the firstN-type transistor and ground and that switches a current of the firstconstant current source in response to an input pulse of a positivepolarity and thus generates the output pulse current. The circuit alsoincludes a first P-type transistor that is connected at a first signalelectrode thereof to the output terminal and that functions as a secondconstant current source according to a bias voltage of a negativepolarity, and a second P-type transistor that is connected to a secondsignal electrode of the first P-type transistor and a power supply andthat switches a current of the second constant current source inresponse to a first correction pulse of a negative polarity appliedthereto at timing of occurrence of an overshoot in the output pulsecurrent and thus generates a first correction pulse current. The circuitfurther includes a third N-type transistor that is connected to a secondsignal electrode of the first N-type transistor and the ground and thatswitches a current of the first constant current source in response to asecond correction pulse of a positive polarity applied thereto at timingof occurrence of an undershoot in the output pulse current and thusgenerates a second correction pulse current.

[0017] The pulse current generation circuit according to still anotheraspect of this invention, includes a first N-type transistor that isconnected at a first signal electrode thereof to an output terminal ofan output pulse current and that functions as a first constant currentsource according to a bias voltage of a positive polarity, and a secondN-type transistor that is connected to a second signal electrode of thefirst N-type transistor and ground and that switches a current of thefirst constant current source in response to an input pulse of apositive polarity and thus generates the output pulse current. Thecircuit also includes a P-type transistor that is connected to a powersupply and the output terminal and that conducts a switching operationin response to a first correction pulse of a negative polarity appliedthereto at timing of occurrence of an overshoot in the output pulsecurrent and thus generates a first correction pulse current, and a thirdN-type transistor that is connected to the output terminal and theground and that conducts a switching operation in response to a secondcorrection pulse of a positive polarity applied thereto at timing ofoccurrence of an undershoot in the output pulse current and thusgenerates a second correction pulse current.

[0018] The pulse current generation circuit according to still anotheraspect of this invention, includes a CMOS inverter that inverts an inputpulse applied thereto and outputs the inverted pulse, a current source,and a current mirror circuit that supplies an output current of thecurrent source to the CMOS inverter. The circuit also includes a firstN-type transistor that is connected at a first signal electrode thereofto an output terminal of an output pulse current and that functions as aconstant current source according to a bias voltage of a positivepolarity, and a second N-type transistor that is connected to a secondsignal electrode of the first N-type transistor and ground and thatswitches a current of the constant current source in response to anoutput of the CMOS inverter and thus generates the output pulse current.

[0019] The pulse current generation circuit according to still anotherinvention, includes first and second N-type transistors that are eachconnected at a first signal electrode thereof to an output terminal ofan output pulse current and that function respectively as first andsecond constant current sources according to a bias voltage of apositive polarity. The circuit also includes a third N-type transistorthat is connected to a second signal electrode of the first N-typetransistor and ground and that switches a current of the first constantcurrent source in response to an input pulse of a positive polarity andthus generates the output pulse current, and a fourth N-type transistorthat is connected to a second signal electrode of the second N-typetransistor and the ground and that conducts a switching operation inresponse to a correction pulse of a positive polarity provided with avalley portion at timing of occurrence of an overshoot in the outputpulse current and with a hill portion at timing of occurrence of anundershoot in the output pulse current, and thus generates a correctionpulse current.

[0020] The pulse current generation circuit according to still anotheraspect of this invention, includes a first N-type transistor that isconnected at a first signal electrode thereof to an output terminal ofan output pulse current and that functions as a first constant currentsource according to a bias voltage of a positive polarity, and a secondN-type transistor that is connected to a second signal electrode of thefirst N-type transistor and ground and that switches a current of thefirst constant current source in response to an input pulse of apositive polarity and thus generates the output pulse current. Thecircuit also includes a third N-type transistor that is connected to theoutput terminal and the ground and that conducts a switching operationin response to a correction pulse of a positive polarity provided with avalley portion at timing of occurrence of an overshoot in the outputpulse current and with a hill portion at timing of occurrence of anundershoot in the output pulse current, and thus generates a correctionpulse current.

[0021] These and other objects, features and advantages of the presentinvention are specifically set forth in or will become apparent from thefollowing detailed descriptions of the invention when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 is a circuit diagram that shows a configuration of a pulsecurrent generation circuit according to a first embodiment of thepresent invention,

[0023]FIG. 2 is a waveform diagram that explains an operation of thepulse current generation circuit shown in FIG. 1,

[0024]FIG. 3 is a circuit diagram that shows a configuration of a pulsecurrent generation circuit according to a second embodiment of thepresent invention,

[0025]FIG. 4 is a circuit diagram that shows a configuration of a pulsecurrent generation circuit according to a third embodiment of thepresent invention,

[0026]FIG. 5 is a circuit diagram that shows a configuration of a pulsecurrent generation circuit according to a fourth embodiment of thepresent invention,

[0027]FIG. 6 is a waveform diagram that explains an operation of thepulse current generation circuit shown in FIG. 5,

[0028]FIG. 7 is a circuit diagram that shows a configuration of a pulsecurrent generation circuit according to a fifth embodiment of thepresent invention,

[0029]FIG. 8 is a waveform diagram that explains an operation of thepulse current generation circuit shown in FIG. 7,

[0030]FIG. 9 is a circuit diagram that shows a configuration of a pulsecurrent generation circuit according to a sixth embodiment of thepresent invention,

[0031]FIG. 10 is a waveform diagram that explains an operation of thepulse current generation circuit shown in FIG. 9,

[0032]FIG. 11 is a circuit diagram that shows a configuration of a pulsecurrent generation circuit according to a seventh embodiment of thepresent invention,

[0033]FIG. 12 is a waveform diagram that shows an operation of the pulsecurrent generation circuit shown in FIG. 11,

[0034]FIG. 13 is a circuit diagram that shows a configuration of a pulsecurrent generation circuit according to an eighth embodiment of thepresent invention,

[0035]FIG. 14 is a waveform diagram that explains an operation of thepulse current generation circuit shown in FIG. 13,

[0036]FIG. 15 is a circuit diagram that shows a configuration of a pulsecurrent generation circuit according to a ninth embodiment of thepresent invention,

[0037]FIG. 16 is a waveform diagram that explains an operation of thepulse current generation circuit shown in FIG. 15,

[0038]FIG. 17 is a circuit diagram that shows a configuration of a pulsecurrent generation circuit according to a tenth embodiment of thepresent invention,

[0039]FIG. 18 is a waveform diagram that explains an operation of thepulse current generation circuit shown in FIG. 17, and

[0040]FIG. 19 is a circuit diagram that shows a configuration example ofa pulse current generation circuit formed of a conventional integratedcircuit.

DETAILED DESCRIPTION

[0041] Embodiments of the pulse current generation circuit according tothe present invention will be explained in detail below with referenceto accompanying drawings.

[0042] A first embodiment of this invention will be explained below.FIG. 1 is a circuit diagram that shows the configuration of a pulsecurrent generation circuit according to the first embodiment. As shownin FIG. 1, the first embodiment of the pulse current generation circuitincludes PMOS transistors 2 and 3 and NMOS transistors 4 and 5 connectedin series between a power supply 1 and ground (GND), NMOS transistors 6and 7 connected in parallel with the NMOS transistors 4 and 5, and biasvoltage sources 8, 9 and 10. A laser diode 13 is connected to an ICoutput terminal 11 and an external power supply 12. The external snubbercircuit 107 shown in FIG. 19 is not provided.

[0043] The PMOS transistor 2 is connected at its source electrode to thepower supply 1, and connected at its drain electrode to the PMOStransistor 3 at its source electrode. A narrow pulse of a negativepolarity (correction pulse “b”) is applied to the PMOS transistor 2 atits gate electrode.

[0044] A bias voltage of a negative polarity from the bias voltagesource 8 is applied to the PMOS transistor 3 at its gate electrode. ThePMOS transistor 3 is connected at its drain electrode to the IC outputterminal 11 and to drain electrodes of the NMOS transistors 4 and 6.

[0045] A bias voltage of a positive polarity from the bias voltagesource 9 is applied to the NMOS transistor 4 at its gate electrode. TheNMOS transistor 4 is connected at its source electrode to the NMOStransistor 5 at its drain electrode. The NMOS transistor 5 is connectedat its source electrode to the ground (GND). An input pulse “a” having apredetermined pulse width is applied to the NMOS transistor 5 at itsgate electrode.

[0046] The NMOS transistor 6 is connected at its source electrode to theNMOS transistor 7 at its drain electrode. The NMOS transistor 7 isconnected at its source electrode to the ground (GND). A bias voltage ofa positive polarity from the bias voltage source 10 is applied to theNMOS transistor 6 at its gate electrode. A narrow pulse of a positivepolarity (correction pulse “c”) is applied to the NMOS transistor 7 atits gate electrode.

[0047] Operation of the pulse current generation circuit of the firstembodiment will now be explained with reference to FIGS. 1 and 2. FIG. 2is a waveform diagram that shows the operation of the pulse currentgeneration circuit shown in FIG. 1.

[0048] The bias voltage of the negative polarity from the bias voltagesource 8 is applied to the gate electrode of the PMOS transistor 3. ThePMOS transistor 3 is in the ON operation state, and the PMOS transistor3 forms a constant current source that flows a preset constant current.A pulse current is output from the PMOS transistor 3 by ON/OFF operationof the PMOS transistor 2.

[0049] The gate electrodes of the NMOS transistors 4 and 6 are suppliedwith the bias voltages of the positive polarity respectively from thebias voltage sources 9 and 10. Each of the NMOS transistors 4 and 6 isthus in the ON operation state, and forms a constant current source thatflows a preset constant current. Pulse currents are output from the NMOStransistors 4 and 6 by ON/OFF operation of the NMOS transistors 5 and 7.

[0050] The input pulse “a” of the positive polarity as shown in (1) ofFIG. 2 is applied to the gate electrode of the NMOS transistor 5. As aresult, the constant current source formed of the NMOS transistor 4 isturned ON/OFF, and a pulse current is generated. As shown in (2) of FIG.2, an overshoot occurs on a rising edge of the waveform of the pulsecurrent (the output current of the NMOS transistor 4) and an undershootoccurs on a falling edge.

[0051] At the overshoot occurrence timing of the output current of theNMOS transistor 4, therefore, a narrow pulse of a negative polarity (thecorrection pulse “b”) as shown in (3) of FIG. 2 is applied to the gateelectrode of the PMOS transistor 2. As a result, a current that has awaveform corresponding to the overshoot that has occurred on the risingedge of the output current of the NMOS transistor 4 is obtained in theoutput current of the PMOS transistor 3 as shown in (4) of FIG. 2. Byadding the output current of the NMOS transistor 4 and the outputcurrent of the PMOS transistor 3 together, the overshoot that hasoccurred on the rising edge of the output current of the NMOS transistor4 is reduced, because currents are added caused by switching of constantcurrent sources in opposite directions.

[0052] At the undershoot occurrence timing of the output current of theNMOS transistor 4, a narrow pulse of a positive polarity (the correctionpulse “c”) as shown in (5) of FIG. 2 is applied to the gate electrode ofthe NMOS transistor 7. As a result, a current that has a waveformcorresponding to the undershoot that has occurred on the falling edge ofthe output current of the NMOS transistor 4 is obtained in the outputcurrent of the NMOS transistor 6 as shown in (6) of FIG. 2. By addingthe output current of the NMOS transistor 4 and the output current ofthe NMOS transistor 6 together, the undershoot that has occurred on thefalling edge of the output current of the NMOS transistor 4 is reduced.

[0053] A composite output pulse current output to the IC output terminal11 has a waveform remarkably improved in overshoot and undershoot asshown in (7) of FIG. 2.

[0054] Thus, in the pulse current generation circuit of the firstembodiment, a pulse current improved in overshoot and undershoot isobtained without using a component provided outside.

[0055] A second embodiment of this invention will be explained below.FIG. 3 is a circuit diagram that shows the configuration of a pulsecurrent generation circuit according to the second embodiment. In FIG.3, components that are the same as or equivalent to the components shownin the first embodiment (FIG. 1) are denoted by like characters. Aportion that concerns the second embodiment will now be explainedmainly.

[0056] As shown in FIG. 3, the pulse current generation circuit of thesecond embodiment is obtained by omitting the NMOS transistor 6 and thebias voltage source 10 in the configuration of the first embodiment(FIG. 1) and connecting the drain electrode of the NMOS transistor 7 toa node between the source electrode of the NMOS transistor 4 and thedrain electrode of the NMOS transistor 5.

[0057] In the first embodiment, the correction current for reducing theundershoot is generated by the NMOS transistor 6 that forms a constantcurrent source. Instead, in the second embodiment, the constant currentsource formed of the NMOS transistor 4 that generates the basic pulsecurrent is utilized and ON resistance connected to the source electrodeof the NMOS transistor 4 is changed.

[0058] In this configuration as well, an operation and an effect similarto those of the first embodiment are obtained. In the second embodiment,it is necessary to optimize the quantity of correction current forundershoot reduction by adjusting the transistor size. Since the NMOStransistors 4 and 7 are connected in a cascade form and the number ofconstant current sources is reduced by one, the slew rate of the outputpulse current is improved as compared with the first embodiment.

[0059] A third embodiment of this invention will be explained below.FIG. 4 is a circuit diagram that shows the configuration of a pulsecurrent generation circuit according to the third embodiment. In FIG. 4,components that are the same as or equivalent to those shown in thefirst embodiment (FIG. 1) are denoted by like characters. A portion thatconcerns the third embodiment will now be explained mainly.

[0060] As shown in FIG. 3, the pulse current generation circuit of thethird embodiment is obtained by providing a variable bias voltage source15 instead of the bias voltage source 8 that concerns the constantcurrent source provided to improve the overshoot in the configurationshown in the first embodiment (FIG. 1) and providing a variable biasvoltage source 16 instead of the bias voltage source 10 that concernsthe constant current source provided to improve the undershoot.

[0061] According to this configuration, the correction currents of theovershoot correction circuit and the undershoot correction circuit canbe varied, and consequently it becomes possible to conduct optimumsetting.

[0062] A fourth embodiment of this invention will be explained below.FIG. 5 is a circuit diagram that shows the configuration of a pulsecurrent generation circuit according to the fourth embodiment. In FIG.5, components that are the same as or equivalent to those shown in thefirst embodiment (FIG. 1) are denoted by like characters. A portion thatconcerns the fourth embodiment will now be explained mainly.

[0063] As shown in FIG. 5, the pulse current generation circuit of thefourth embodiment has the same configuration as that of the firstembodiment (FIG. 1). There are difference points that a correction pulse“d” is used instead of the correction pulse “b” as the correction pulseof the negative polarity applied to the gate electrode of the PMOStransistor 2, and that a correction pulse “e” is used instead of thecorrection pulse “c” as the correction pulse of the positive polarityapplied to the gate electrode of the NMOS transistor 7.

[0064] The correction pulse “d” includes a first pulse d1 that has awide pulse width and a second pulse d2 that has a narrow pulse width.The first pulse d1 is applied at the timing of occurrence of theovershoot, which appears in the output pulse current. The second pulsed2 is applied at the timing of occurrence of the undershoot.

[0065] The correction pulse “e” includes a first pulse e1 that has anarrow pulse width and a second pulse e2 that has a wide pulse width.The first pulse e1 is applied at the timing of occurrence of theovershoot, which appears in the output pulse current. The second pulsee2 is applied at the timing of occurrence of the undershoot.

[0066] Operation of the pulse current generation circuit of the fourthembodiment will now be explained with reference to FIGS. 5 and 6. FIG. 6is a waveform diagram that shows the operation of the pulse currentgeneration circuit shown in FIG. 5.

[0067] The bias voltage of the negative polarity from the bias voltagesource 8 is applied to the gate electrode of the PMOS transistor 3. ThePMOS transistor 3 is in the ON operation state, and the PMOS transistor3 forms a constant current source that flows a preset constant current.A pulse current is output from the PMOS transistor 3 by ON/OFF operationof the PMOS transistor 2.

[0068] The gate electrodes of the NMOS transistors 4 and 6 are appliedwith the bias voltages of the positive polarity respectively from thebias voltage sources 9 and 10. Each of the NMOS transistors 4 and 6 isthus in the ON operation state, and forms a constant current source thatflows a preset constant current. Pulse currents are output from the NMOStransistors 4 and 6 by ON/OFF operation of the NMOS transistors 5 and 7.

[0069] The input pulse “a” of the positive polarity as shown in (1) ofFIG. 6 is applied to the gate electrode of the NMOS transistor 5. As aresult, the constant current source formed of the NMOS transistor 4 isturned ON/OFF to generate a pulse current. As shown in (3) of FIG. 6, anovershoot occurs on a rising edge of the waveform of the pulse current(the output current of the NMOS transistor 4) and an undershoot occurson a falling edge thereof.

[0070] The correction pulse “e” that has a waveform shown in (8) of FIG.6 is applied to the gate electrode of the NMOS transistor 7. Thecorrection pulse “d” that has a waveform shown in (9) of FIG. 6 isapplied to the gate electrode of the PMOS transistor 2. On a rising edgeof the input pulse “a”, the following operation is conducted.

[0071] The first pulse e1 of the correction pulse “e” rises insynchronism with the rising edge of the input pulse “a”. The first pulsee1 has a waveform that falls immediately after the input pulse “a” hasrisen and that is comparatively narrow in pulse width. An output currentof the NMOS transistor 6 as represented by 7 a in (7) of FIG. 6 isgenerated by the first pulse e1.

[0072] On the other hand, the first pulse d1 of the correction pulse “d”has a waveform that falls after a rising edge of the first pulse e1 andrises when a certain time of period has elapsed after the rising of theinput pulse “a” and that is comparatively wide in pulse width. An outputcurrent of the PMOS transistor 3 as represented by 6 a in (6) of FIG. 6is generated by the first pulse d1.

[0073] Since the first pulse e1 is applied before the first pulse d1,the output current 7 a generated by the first pulse e1 is added to acurrent generated by the input pulse “a” and shown in (3) of FIG. 6, asa speed-up current 5 a shown in (5) of FIG. 6. The generation timing ofthe speed-up current 5 a precedes the generation timing of theovershoot. As shown in (2) of FIG. 6, therefore, the rising edge of theoutput pulse current becomes steep and the waveform becomes such thatthe overshoot quantity increases.

[0074] Thereafter, the output current 6 a generated by the first pulsed1 is added to the output pulse current increased in overshoot quantity((2) of FIG. 6) as an overshoot improvement current 4 a shown in (4) ofFIG. 6. The pulse width of the first pulse d1 is made wide to such adegree that a current quantity required to reduce the overshoot isobtained.

[0075] The first pulse e1 and the first pulse d1 overlap each other.There is a time period during which the NMOS transistor 7 and the PMOStransistor 2 are in the ON state simultaneously. Therefore, the speed-upin the rising and the overshoot reduction are executed as a series ofconsecutive, operations.

[0076] On a falling edge of the input pulse “a”, the following operationis conducted. The second pulse d2 of the correction pulse “d” has awaveform that falls in synchronism with the falling edge of the inputpulse “a” and rises immediately after the input pulse “a” has fallen andthat is comparatively narrow in pulse width. An output current of thePMOS transistor 3 as represented by 6 b in (6) of FIG. 6 is generated bythe second pulse d2.

[0077] On the other hand, the second pulse e2 of the correction pulse“e” has a waveform that rises after a falling edge of the second pulsed2 and falls when a certain time of period has elapsed after the fallingof the input pulse “a” and that is comparatively wide in pulse width. Anoutput current of the NMOS transistor 6 as represented by 7 b in (7) ofFIG. 6 is generated by the second pulse e2.

[0078] Since the second pulse d2 is applied before the second pulse e2,the output current 6 b generated by the second pulse d2 is added to acurrent generated by the input pulse “a” and shown in (3) of FIG. 6, asa speed-up current 5 b shown in (5) of FIG. 6. The generation timing ofthe speed-up current 5 b precedes the generation timing of theundershoot. As shown in (2) of FIG. 6, therefore, the falling edge ofthe output pulse current becomes steep and the waveform becomes suchthat the undershoot quantity increases.

[0079] Thereafter, the output current 7 b generated by the second pulsee2 is added to the output pulse current increased in undershoot quantity((2) of FIG. 6) as an undershoot improvement current 4 b shown in (4) ofFIG. 6. The pulse width of the second pulse e2 is made wide to such adegree that a current quantity required to reduce the undershoot isobtained.

[0080] The second pulse e2 and the second pulse d2 overlap each other.There is a time period during which the NMOS transistor 7 and the PMOStransistor 2 are in the ON state simultaneously. Therefore, the speed-upin the falling and the undershoot reduction are executed as a series ofconsecutive operations.

[0081] Thus, in the pulse current generation circuit of the fourthembodiment, the slew rate of the composite output pulse current waveformis increased in addition to the improvement of the overshoot andundershoot.

[0082] A fifth embodiment of this invention will be explained below.FIG. 7 is a circuit diagram that shows the configuration of a pulsecurrent generation circuit according to the fifth embodiment. As shownin FIG. 7, the pulse current generation circuit includes PMOS transistor21 and NMOS transistors 22 and 23 connected in series between the powersupply 1 and the ground (GND), an NMOS transistor 24 connected inparallel with the NMOS transistors 22 and 23, and a bias voltage source25. A laser diode 13 is connected between an IC output terminal 11 andan external power supply 12. The external snubber circuit 107 as shownin FIG. 19 is not provided.

[0083] The PMOS transistor 21 is connected at its source electrode tothe power supply 1, and connected at its drain electrode to the ICoutput terminal 11 and to drain electrodes of the NMOS transistors 22and 24. A narrow pulse of a negative polarity (correction pulse “b”) isapplied to the PMOS transistor 21 at its gate electrode.

[0084] A bias voltage of a positive polarity from the bias voltagesource 25 is applied to the NMOS transistor 22 at its gate electrode.The NMOS transistor 22 is connected at its source electrode to the NMOStransistor 23 at its drain electrode. The NMOS transistor 23 isconnected at its source electrode to the ground (GND). An input pulse“a” having a predetermined pulse width is applied to the NMOS transistor23 at its gate electrode. The NMOS transistor 24 is connected at itssource electrode to the ground (GND). A narrow pulse of a positivepolarity (correction pulse “c”) is applied to the NMOS transistor 24 atits gate electrode.

[0085] In short, as understood from comparison with FIG. 1, the pulsecurrent generation circuit has a configuration obtained by omitting thePMOS transistor 3, the bias voltage source 8, the NMOS transistor 6, andthe bias voltage source 10 from the pulse current generation circuit ofthe first embodiment.

[0086] Operation of the pulse current generation circuit of the fifthembodiment will now be explained with reference to FIGS. 7 and 8. FIG. 8is a waveform diagram that explains the operation of the pulse currentgeneration circuit shown in FIG. 7.

[0087] The bias voltage of the positive polarity from the bias voltagesource 25 is applied to the gate electrode of the NMOS transistor 22.The NMOS transistor 22 is in the ON operation state, and the NMOStransistor 22 forms a constant current source that flows a presetconstant current.

[0088] The input pulse “a” of the positive polarity as shown in (1) ofFIG. 8 is applied to the gate electrode of the NMOS transistor 23. As aresult, the constant current source formed of the NMOS transistor 22 isturned ON/OFF, and a pulse current is generated. As shown in (2) of FIG.8, an overshoot occurs on a rising edge of the waveform of the pulsecurrent (the output current of the NMOS transistor 22) and an undershootoccurs on a falling edge.

[0089] At the overshoot occurrence timing of the output current of theNMOS transistor 22, therefore, a narrow pulse of a negative polarity(the correction pulse “b”) as shown in (3) of FIG. 8 is applied to thegate electrode of the PMOS transistor 21. As a result, a current thathas a waveform corresponding to the overshoot that has occurred on therising edge of the output current of the NMOS transistor 22 is obtainedin the output current of the PMOS transistor 21 as shown in (4) of FIG.8. By adding the output current of the NMOS transistor 22 and the outputcurrent of the PMOS transistor 21 together, the overshoot that hasoccurred on the rising edge of the output current of the NMOS transistor22 is reduced, because currents caused by switching in oppositedirections are added.

[0090] At the undershoot occurrence timing of the output current of theNMOS transistor 22, a narrow pulse of a positive polarity (thecorrection pulse “c”) as shown in (5) of FIG. 8 is applied to the gateelectrode of the NMOS transistor 24. As a result, a current that has awaveform corresponding to the undershoot that has occurred on thefalling edge of the output current of the NMOS transistor 22 is obtainedin the output current of the NMOS transistor 24 as shown in (6) of FIG.8. By adding the output current of the NMOS transistor 22 and the outputcurrent of the NMOS transistor 24 together, the undershoot that hasoccurred on the falling edge of the output current of the NMOStransistor 22 is reduced.

[0091] A composite output pulse current output to the IC output terminal11 has a waveform remarkably improved in overshoot and undershoot asshown in (7) of FIG. 8.

[0092] When forming a constant current source by using a MOS transistor,the transistor size becomes large, resulting in increased parasiticcapacitance. In the first embodiment (FIG. 1), a current drawn when thePMOS transistor 2 turns ON and a current that charges the parasiticcapacitance when the PMOS transistor 2 turns OFF need to be large. Inthe first embodiment (FIG. 1), therefore, it is difficult to improve theslew rate. Further, there is a drawback of an increased number ofcomponents to the configuration of first embodiment (FIG. 1).

[0093] In the fifth embodiment, the constant current source formed ofthe PMOS transistor 3 shown in the first embodiment (FIG. 1) is omitted,and a current that improves the overshoot is generated by the ON/OFFoperation of the PMOS transistor 21. As a result, the number ofcomponents can be reduced and the slew rate can be made high.

[0094] A sixth embodiment of this invention will be explained below.FIG. 9 is a circuit diagram that shows the configuration of a pulsecurrent generation circuit according to the sixth embodiment. In FIG. 9,components that are the same as or equivalent to those shown in thefifth embodiment (FIG. 7) are denoted by like characters. A portion thatconcerns the sixth embodiment will now be explained mainly.

[0095] As shown in FIG. 9, the pulse current generation circuit of thesixth embodiment has the same configuration as that of the fifthembodiment (FIG. 7). A different point in the configuration from that ofthe fifth embodiment is that a correction pulse “d” is used instead ofthe correction pulse “b” as the correction pulse of the negativepolarity applied to the gate electrode of the PMOS transistor 21 and acorrection pulse “e” is used instead of the correction pulse “c” as thecorrection pulse of the positive polarity applied to the gate electrodeof the NMOS transistor 24.

[0096] The correction pulse “e” includes a first pulse e1 that has anarrow pulse width and a second pulse e2 that has a wide pulse width.The first pulse e1 is applied at the timing of occurrence of theovershoot, which appears in the output pulse current. The second pulsee2 is applied at the timing of occurrence of the undershoot.

[0097] Operation of the pulse current generation circuit of the sixthembodiment will now be explained with reference to FIGS. 9 and 10. FIG.10 is a waveform diagram that shows the operation of the pulse currentgeneration circuit shown in FIG. 9.

[0098] The bias voltage of the positive polarity from the bias voltagesource 25 is applied to the gate electrode of the NMOS transistor 22.The NMOS transistor 22 is in the ON operation state, and the NMOStransistor 22 forms a constant current source that flows a presetconstant current.

[0099] The input pulse “a” of the positive polarity as shown in (1) ofFIG. 10 is applied to the gate electrode of the NMOS transistor 23. As aresult, the constant current source formed of the NMOS transistor 22 isturned ON/OFF, and a pulse current is generated. As shown in (3) of FIG.10, an overshoot occurs on a rising edge of the waveform of the pulsecurrent (the output current of the NMOS transistor 22) and an undershootoccurs on a falling edge.

[0100] The correction pulse “e” that has a waveform shown in (8) of FIG.10 is applied to the gate electrode of the NMOS transistor 24. Thecorrection pulse “d” that has a waveform shown in (9) of FIG. 10 isapplied to the gate electrode of the PMOS transistor 21. On a risingedge of the input pulse “a”, the following operation is conducted.

[0101] The first pulse e1 of the correction pulse “e” rises insynchronism with the rising edge of the input pulse “a”. The first pulsee1 has a waveform that falls immediately after the input pulse “a” hasrisen and that is comparatively narrow in pulse width. An output currentof the NMOS transistor 24 as represented by 7 a in (7) of FIG. 10 isgenerated by the first pulse e1.

[0102] On the other hand, the first pulse d1 of the correction pulse “d”has a waveform that falls after a rising edge of the first pulse e1 andrises when a certain time of period has elapsed after the rising of theinput pulse “a” and that is comparatively wide in pulse width. An outputcurrent of the PMOS transistor 21 as represented by 6 a in (6) of FIG.10 is generated by the first pulse d1.

[0103] Since the first pulse e1 is applied before the first pulse d1,the output current 7 a generated by the first pulse e1 is added to acurrent generated by the input pulse “a” shown in (3) of FIG. 10, as aspeed-up current 5 a shown in (5) of FIG. 10. The generation timing ofthe speed-up current 5 a precedes the generation timing of theovershoot. As shown in (2) of FIG. 10, therefore, the rising edge of theoutput pulse current becomes steep and the waveform becomes such thatthe overshoot quantity increases.

[0104] Thereafter, the output current 6 a generated by the first pulsed1 is added to the output pulse current increased in overshoot quantity((2) of FIG. 10) as an overshoot improvement current 4 a shown in (4) ofFIG. 10. The pulse width of the first pulse d1 is made wide to such adegree that a current quantity required to reduce the overshoot isobtained.

[0105] The first pulse e1 and the first pulse d1 overlap each other.There is a time period during which the NMOS transistor 24 and the PMOStransistor 21 are in the ON state simultaneously. Therefore, thespeed-up in the rising and the overshoot reduction are executed as aseries of consecutive operations.

[0106] On the falling edge of the input pulse “a”, the followingoperation is conducted. The second pulse d2 of the correction pulse “d”has a waveform that falls in synchronism with the falling edge of theinput pulse “a” and rises immediately after the input pulse “a” hasfallen and that is comparatively narrow in pulse width. An outputcurrent of the NMOS transistor 21 as represented by 6 b in (6) of FIG.10 is generated by the second pulse d2.

[0107] On the other hand, the second pulse e2 of the correction pulse“e” has a waveform that falls after the falling edge of the second pulsed2 and falls when a certain time of period has elapsed after the fallingof the input pulse “a” and that is comparatively wide in pulse width. Anoutput current of the NMOS transistor 24 as represented by 7 b in (7) ofFIG. 10 is generated by the second pulse e2.

[0108] Since the second pulse d2 is applied before the second pulse e2,the output current 6 b generated by the second pulse d2 is added to acurrent generated by the input pulse “a” shown in (3) of FIG. 10, as aspeed-up current 5 b shown in (5) of FIG. 10. The generation timing ofthe speed-up current 5 b precedes the generation timing of theundershoot. As shown in (2) of FIG. 10, therefore, the falling edge ofthe output pulse current becomes steep and the waveform becomes suchthat the undershoot quantity increases.

[0109] Thereafter, the output current 7 b generated by the second pulsee2 is added to the output pulse current increased in undershoot quantity((2) of FIG. 10) as an undershoot improvement current 4 b shown in (4)of FIG. 10. The pulse width of the second pulse e2 is made wide to sucha degree that a current quantity required to reduce the undershoot isobtained.

[0110] The second pulse e2 and the second pulse d2 overlap each other.There is a time period during which the NMOS transistor 24 and the PMOStransistor 21 are in the ON state simultaneously. Therefore, thespeed-up in the falling and the undershoot reduction are executed as aseries of consecutive operations.

[0111] Thus, in the pulse current generation circuit of the sixthembodiment, the slew rate of the composite output pulse current waveformis increased in addition to the improvement of the overshoot andundershoot.

[0112] A seventh embodiment of this invention will be explained below.FIG. 11 is a circuit diagram that shows the configuration of a pulsecurrent generation circuit according to the seventh embodiment. In FIG.11, a current source 31 and source electrodes of PMOS transistors 32 and33 which form a current mirror circuit, are connected to a line of apower supply 1. NMOS transistors 34, 35 and 38 connected at their sourceelectrodes to ground (GND) form another current mirror circuit.

[0113] An output terminal of the current source 31 is connected to thediode-connected NMOS transistor 34 at its drain electrode and to theNMOS transistor 38 at its gate electrode. The NMOS transistor 35 isconnected at its drain electrode to the diode-connected PMOS transistor32 at its drain electrode.

[0114] The PMOS transistor 33 is connected at its drain electrode to aPMOS transistor 36 at its source electrode. The PMOS transistor 36 isconnected at its drain electrode to an NMOS transistor 37 at its drainelectrode, and connected to an NMOS transistor 40 at its gate electrode.Gate electrodes of the PMOS transistor 36 and the NMOS transistor 37 areconnected in common to serve as an input terminal. In other words, thePMOS transistor 36 and the NMOS transistor 37 form a CMOS inverter.

[0115] The NMOS transistor 37 is connected at its source electrode tothe NMOS transistor 38 at its drain electrode. An NMOS transistor 40 isconnected at its source electrode to ground (GND). The NMOS transistor40 is connected at its drain electrode to an NMOS transistor 39 at itssource electrode. The NMOS transistor 39 is connected at its drainelectrode to the IC output terminal 11. The NMOS transistor 39 isapplied at its gate electrode with a bias voltage of a positive polarityfrom a bias voltage source 48. The laser diode 13 is connected to the ICoutput terminal 11 and the external power supply 12. The externalsnubber circuit 107 shown in FIG. 19 is not provided.

[0116] Operation of the pulse current generation circuit of the seventhembodiment will now be explained with reference to FIGS. 11 and 12. FIG.12 is a waveform diagram that shows the operation of the pulse currentgeneration circuit shown in FIG. 11.

[0117] An output current of the current source 31 is supplied to theinverter formed of the PMOS transistor 36 and the NMOS transistor 37 viathe current mirror circuit formed of the NMOS transistors 34, 35 and 38and another current mirror circuit formed of the PMOS transistors 32 and33.

[0118] An input pulse f is applied to an input terminal of the CMOSinverter (the PMOS transistor 36 and the NMOS transistor 37). The inputpulse f falls from a high level to a low level, stays at the low levelfor a predetermined period of time, and then rises to the high level. Anoutput of the CMOS inverter formed of the PMOS transistor 36 and theNMOS transistor 37 is applied to the gate electrode of the NMOStransistor 40. As a result, the NMOS transistor 40 turns ON/OFF.

[0119] The bias voltage of the positive polarity from the bias voltagesource 48 is applied to the gate electrode of the NMOS transistor 39.The NMOS transistor 39 is thus in the ON operation state, and forms aconstant current source that flows a preset constant current. A pulsecurrent is generated by the ON/OFF operation of the NMOS transistor 40.

[0120] When the input terminal of the CMOS inverter formed of the PMOStransistor 36 and the NMOS transistor 37 is at a high level, the PMOStransistor 36 is in the OFF operation state and the NMOS transistor 37is in the ON operation state. Since the NMOS transistor 38 is in the ONoperation state, the NMOS transistor 40 maintains the OFF operationstate.

[0121] When the input terminal is at a low level, the NMOS transistor 37is in the OFF operation state and the PMOS transistor 36 is in the ONoperation state. Therefore, the NMOS transistor 40 is in the ONoperation state.

[0122] One of causes of the overshoot and undershoot is that the slewrate of the input pulse is too high. When the slew rate of the inputpulse is too high, the impedance caused by the high frequency componentof the output pulse current and inductance becomes high. Thus, counterelectromotive force is generated by the output pulse current, and theovershoot and the undershoot occur.

[0123] In the seventh embodiment, therefore, it is made possible toincrease and decrease current quantities of the current source 31, thecurrent mirror circuit formed of the PMOS transistors 32 and 33, andanother current mirror circuit formed of the NMOS transistors 34, 35 and38. As a result, it becomes possible to effect an adjustment on theswitching speed of the NMOS transistor 40 in order to decrease thesteepness of the rising edge and falling edge of the input waveform ofthe NMOS transistor 40 to such a degree that the overshoot andundershoot do not occur.

[0124] To be concrete, when the current quantities of the current source31 and so on have been adjusted so as to make the input waveform of theNMOS transistor 40 become a waveform that has a gentle rising edge asindicated by (a) in (1) of FIG. 12, the overshoot and undershoot do notappear in the waveform of the output current of the NMOS transistor 39as shown in (3) of FIG. 12.

[0125] On the other hand, when the current quantities of the currentsource 31 and so on have been adjusted so as to make the input waveformof the NMOS transistor 40 become a waveform that has a sharp rising edgeas indicated by (b) in (1) of FIG. 12, the overshoot and undershootappear in the waveform of the output current of the NMOS transistor 39as shown in (2) of FIG. 12.

[0126] Thus, in the pulse current generation circuit of the seventhembodiment, an output pulse current improved remarkably in overshoot andundershoot is obtained by adjusting the current quantities of thecurrent source 31, the current mirror circuit formed of the PMOStransistors 32 and 33, and the current mirror circuit formed of the NMOStransistors 34, 35 and 38. Further, since a PMOS transistor is not usedin the output section, the slew rate is not aggravated.

[0127] An eighth embodiment of this invention will be explained below.FIG. 13 is a circuit diagram that shows the configuration of a pulsecurrent generation circuit according to the eighth embodiment. As shownin FIG. 13, the pulse current generation circuit of the eighthembodiment includes NMOS transistors 41, 42, 43 and 44 and a biasvoltage source 45. The laser diode 13 is connected to the IC outputterminal 11 and the external power supply 12. The external snubbercircuit shown in FIG. 19 is not provided.

[0128] The NMOS transistors 41 and 42 are connected at their drainelectrodes to the IC output terminal 11. A bias voltage of a positivepolarity from a common bias voltage source 45 is applied to gateelectrodes of the NMOS transistors 41 and 42. In other words, each ofthe NMOS transistors 41 and 42 forms a constant current source.

[0129] The NMOS transistor 43 is connected at its drain electrode to theNMOS transistor 41 at its source electrode. The NMOS transistor 43 isconnected at its source electrode to ground (GND). An input pulse “a” isapplied to the NMOS transistor 43 at its gate electrode.

[0130] The NMOS transistor 44 is connected at its drain electrode to theNMOS transistor 42 at its source electrode. The NMOS transistor 44 isconnected at its source electrode to the ground (GND). A correctionpulse “h” is applied to the NMOS transistor 44 at its gate electrode.

[0131] The correction pulse “h” rises on its front edge of the pulse,then falls, and rises again to form a valley portion h1. On its rearedge, the correction pulse “h” falls, then rises, and falls again toforma hill portion h2. The valley portion h1 is formed in the regionwhere overshoot occurs, and the hill portion h2 is formed in the regionwhere undershoot occurs.

[0132] Operation of the pulse current generation circuit of the eighthembodiment will now be explained with reference to FIGS. 13 and 14. FIG.14 is a waveform diagram that explains the operation of the pulsecurrent generation circuit shown in FIG. 13.

[0133] The gate electrodes of the NMOS transistors 41 and 42 are appliedwith the bias voltage of the positive polarity from the common biasvoltage source 45. Each of the NMOS transistors 41 and 42 is thus in theON operation state, and forms a constant current source. Pulse currentsare output from the NMOS transistors 41 and 42 by ON/OFF operation ofthe NMOS transistors 43 and 44. Output pulse currents of the NMOStransistors 41 and 42 are combined and output to the IC output terminal11.

[0134] The input pulse “a” of the positive polarity as shown in (1) ofFIG. 14 is applied to the gate electrode of the NMOS transistor 43. As aresult, the constant current source formed of the NMOS transistor 41 isturned ON/OFF, and a pulse current is generated. As shown in (2) of FIG.14, an overshoot occurs on a rising edge of the waveform of the pulsecurrent (the output current of the NMOS transistor 41) and an undershootoccurs on a falling edge.

[0135] The correction pulse “h” that has a waveform shown in (3) of FIG.14 is applied to the gate electrode of the NMOS transistor 41. Thecorrection pulse “h” rises in synchronism with a rising edge of theinput pulse “a”. At immediately subsequent timing of overshootoccurrence, the correction pulse “h” falls, and then rises again insynchronism with the timing of overshoot termination. On the front edgeof the pulse, the valley portion hi is thus formed in the region of theovershoot occurrence.

[0136] As shown in (2) and (4) of FIG. 14, therefore, the output currentof the NMOS transistor 42 that corresponds to the front edge section ofthe correction pulse “h” becomes opposite in phase to the overshootsection of the output current of the NMOS transistor 41. In the pulsecurrent obtained by combining the output currents of the NMOStransistors 41 and 42, therefore, the overshoot is reduced.

[0137] As shown in (3) of FIG. 14, the correction pulse “h” falls onceon it rear edge in synchronism with a falling edge of the input pulse“a”. At immediately subsequent timing of undershoot occurrence, thecorrection pulse “h” rises, and then falls again in synchronism with thetiming of undershoot termination. As a result, the hill portion h2 isformed.

[0138] As shown in (2) and (4) of FIG. 14, therefore, the output currentof the NMOS transistor 42 that corresponds to the rear edge section ofthe correction pulse “h” becomes opposite in phase to the undershootsection of the output current of the NMOS transistor 41. In the pulsecurrent obtained by combining the output currents of the NMOStransistors 41 and 42, therefore, the undershoot is reduced.

[0139] In the pulse current generation circuit of the eighth embodiment,it becomes possible to conduct correction of the overshoot andundershoot with neither an excess nor insufficiency by adjusting thetransistor sizes of the NMOS transistors 41 and 42 that form theconstant current sources so as to obtain desired DC current values.Further, since a PMOS transistor is not used in the output section, theslew rate is not aggravated.

[0140] A ninth embodiment of this invention will be explained below.FIG. 15 is a circuit diagram that shows the configuration of a pulsecurrent generation circuit according to the ninth embodiment. In FIG.15, components that are the same as or equivalent to those shown in theeighth embodiment (FIG. 13) are denoted by like characters. A portionthat concerns the ninth embodiment will now be explained mainly.

[0141] As shown in FIG. 15, the pulse current generation circuit of theninth embodiment has the same configuration as that of the eighthembodiment (FIG. 13) except that the NMOS transistors 41 and 42 areprovided with respective bias voltage sources. That is, the NMOStransistor 41 is provided with the fixed valued bias voltage source 45shown in the eighth embodiment (FIG. 13), and the NMOS transistor 42 isprovided with a variable bias voltage source 47.

[0142] Operation of the pulse current generation circuit of the ninthembodiment will now be explained with reference to FIGS. 15 and 16. FIG.16 is a waveform diagram that shows the operation of the pulse currentgeneration circuit shown in FIG. 15.

[0143] A bias voltage of a fixed value and a positive polarity from thebias voltage source 45 is applied to the gate electrode of the NMOStransistor 41. The NMOS transistor 41 is in the ON operation state, andthe NMOS transistor 41 forms a constant current source of a fixed value.On the other hand, a variably set bias voltage of a positive polarityfrom the variable bias voltage source 47 is applied to the gateelectrode of the NMOS transistor 42. The NMOS transistor 42 is in the ONoperation state, and the NMOS transistor 42 forms a variable constantcurrent source. Pulse currents are output from the NMOS transistors 41and 42 by ON/OFF operation of the NMOS transistors 43 and 44,respectively. The output pulse currents of the NMOS transistors 41 and42 are combined and output to the IC output terminal 11.

[0144] Operation of the ninth embodiment is similar to that of theeighth embodiment (FIG. 14). In FIG. 16, (1) shows an input waveform(input pulse “a”) of the NMOS transistor 43, (2) shows an output currentwaveform of the NMOS transistor 41, (3) shows an input waveform(correction pulse “h”) of the NMOS transistor 44, (4) shows an outputcurrent waveform of the NMOS transistor 42, and (5) shows an outputpulse current waveform obtained by combining the output current of theNMOS transistor 41 and the output current of the NMOS transistor 42.

[0145] In the ninth embodiment, it becomes possible to conductcorrection of the overshoot and undershoot with neither an excess norinsufficiency by adjusting the bias voltage of the variable bias voltagesource 47 and thereby suitably setting and operating the correctioncurrent quantity of the NMOS transistor 42, which forms a constantcurrent source, i.e., the amplitude level of the waveform shown in (4)of FIG. 16.

[0146] Thus, in the pulse current generation circuit of the ninthembodiment, the correction current is made adjustable and consequentlythe overshoot and undershoot correction can be effected arbitrarily evenduring its use.

[0147] A tenth embodiment of this invention will be explained below.FIG. 17 is a circuit diagram that shows the configuration of a pulsecurrent generation circuit according to the tenth embodiment. In FIG.17, components that are the same as or equivalent to those shown in theeighth embodiment (FIG. 13) are denoted by like characters. A portionthat concerns the tenth embodiment will now be explained mainly.

[0148] As shown in FIG. 17, the pulse current generation circuit of thetenth embodiment has the same configuration as that of the eighthembodiment (FIG. 13) except that the NMOS transistor 42 is omitted andthe drain electrode of the NMOS transistor 44 is connected to the ICoutput terminal 11 together with the drain electrode of the NMOStransistor 41.

[0149] In other words, the correction current is generated by only ONresistance of the NMOS transistor 44. A required correction currentquantity is determined by adjusting the transistor size of the NMOStransistor 44, which conducts the switching operation according to thecorrection pulse “h”.

[0150] Operation of the pulse current generation circuit of the tenthembodiment will now be explained with reference to FIGS. 17 and 18. FIG.18 is a waveform diagram that shows the operation of the pulse currentgeneration circuit shown in FIG. 17.

[0151] The operation of the tenth embodiment is similar to that of theeighth embodiment (FIG. 14). In FIG. 18, (1) shows an input waveform(input pulse “a”) of the NMOS transistor 43, (2) shows an output currentwaveform of the NMOS transistor 41, (3) shows an input waveform(correction pulse “h”) of the NMOS transistor 44, (4) shows an outputcurrent waveform of the NMOS transistor 44, and (5) shows an outputpulse current waveform obtained by combining the output current of theNMOS transistor 41 and the output current of the NMOS transistor 44.

[0152] In the pulse current generation circuit of the tenth embodiment,it becomes possible to conduct correction of the overshoot andundershoot with neither an excess nor insufficiency by adjusting thetransistor sizes of the NMOS transistor that conducts the switchingoperation according to the correction pulse so as to obtain a desired DCcurrent value. Further, since a PMOS transistor is not used in theoutput section, the slew rate is not aggravated. In addition, the numberof components can be reduced.

[0153] In the respective embodiments, the pulse current generationcircuits formed of the MOS transistors are shown and configurationsusing bipolar transistors have been omitted. However, it is a matter ofcourse that any of the first to six and eighth to tenth embodiments canbe formed of bipolar transistors as well.

[0154] As heretofore explained, according to the one aspect of theinvention, the first N-type transistor connected at the first signalelectrode thereof to the output terminal of an output pulse currentfunctions as the first constant current source according to a biasvoltage of the positive polarity. The second N-type transistor connectedto the second signal electrode of the first N-type transistor and groundswitches a current of the first constant current source in response tothe input pulse of the positive polarity and thus generates the outputpulse current where an overshoot and an undershoot appear. Therefore,the first P-type transistor connected at the first signal electrodethereof to the output terminal is made to function as the secondconstant current source according to the bias voltage of the negativepolarity. The first correction pulse of the negative polarity is appliedto the second P-type transistor connected to the second signal electrodeof the first P-type transistor and the power supply at timing ofoccurrence of the overshoot in the output pulse current in order toswitch the current of the second constant current source and thusgenerate the first correction pulse current. As a result, the firstcorrection current and the output pulse current are added together.Thus, the output pulse current improved in overshoot is output from theoutput terminal. Further, the third N-type transistor connected at thefirst signal electrode thereof to the output terminal is made tofunction as the third constant current source according to the biasvoltage of the positive polarity. The second correction pulse of thepositive polarity is applied to the fourth N-type transistor connectedto the second signal electrode of the third N-type transistor and groundat timing of occurrence of the undershoot in the output pulse current inorder to switch the current of the third constant current source andthus generate the second correction pulse current. As a result, thesecond correction pulse current and the output pulse current are addedtogether. Thus, the output pulse current improved in undershoot isoutput from the output terminal. Since the overshoot and undershoot canbe thus improved without requiring any external component, a higher slewrate can be achieved.

[0155] According to the another aspect of the invention, the firstN-type transistor connected at the first signal electrode thereof to theoutput terminal of an output pulse current functions as the firstconstant current source according to the bias voltage of the positivepolarity. The second N-type transistor connected tow the second signalelectrode of the first N-type transistor and ground switches the currentof the first constant current source in response to an input pulse ofthe positive polarity and thus generates the output pulse current. Anovershoot and an undershoot appear on the output pulse current.Therefore, the first P-type transistor connected at the first signalelectrode thereof to the output terminal is made to function as thesecond constant current source according to the bias voltage of thenegative polarity. The first correction pulse of the negative polarityis applied to the second P-type transistor connected to the secondsignal electrode of the first P-type transistor and the power supply attiming of occurrence of the overshoot in the output pulse current inorder to switch the current of the second constant current source andthus generate the first correction pulse current. As a result, the firstcorrection current and the output pulse current are added together.Thus, the output pulse current improved in overshoot is output from theoutput terminal. Further, the second correction pulse of the positivepolarity is applied to the third N-type transistor connected to thesecond signal electrode of the first N-type transistor and ground attiming of occurrence of the undershoot in the output pulse current inorder to switch the current of the first constant current source andthus generate the second correction pulse current. As a result, thesecond correction pulse current and the output pulse current are addedtogether. Thus, the output pulse current improved in undershoot isoutput from the output terminal. Since the overshoot and undershoot canbe thus improved without requiring any external component, a higher slewrate can be achieved.

[0156] Moreover, each of the first P-type transistor and the thirdN-type transistor receives a variable bias voltage from the variablebias voltage source to form the variable constant current source. As aresult, the correction pulse current can be adjusted. Therefore,appropriate improvement of the overshoot and undershoot can be effected.

[0157] According to the still another aspect of the invention, the firstN-type transistor connected at the first signal electrode thereof to theoutput terminal of an output pulse current functions as the firstconstant current source according to the bias voltage of the positivepolarity. The second N-type transistor connected to the second signalelectrode of the first N-type transistor and ground switches a currentof the first constant current source in response to the input pulse ofthe positive polarity and thus generates the output pulse current, wherean overshoot and an undershoot appear. Therefore, the first correctionpulse of the negative polarity is applied to the P-type transistorconnected to the power supply and the output terminal at timing ofoccurrence of the overshoot in the output pulse current in order toswitch the current of the second constant current source and thusgenerate the first correction pulse current. As a result, the firstcorrection current and the output pulse current are added together.Thus, the output pulse current improved in overshoot is output from theoutput terminal. Further, the second correction pulse of the positivepolarity is applied to the third N-type transistor connected to theoutput terminal and the ground at timing of occurrence of the undershootin the output pulse current in order to conduct the switching operationand thus generate the second correction pulse current. As a result, thesecond correction pulse current and the output pulse current are addedtogether. Thus, the output pulse current improved in undershoot isoutput from the output terminal. Since the overshoot and undershoot canbe thus improved without requiring any external component, a higher slewrate can be achieved.

[0158] Furthermore, the first correction pulse includes two negativepulses. One of the pulses has a wide pulse width generated at timing ofoccurrence of the overshoot in the output pulse current, and the otherhas a narrow pulse width generated at timing of occurrence of theundershoot. The second correction pulse includes two positive pulses.One of the pulses has a narrow pulse width generated at timing ofoccurrence of the overshoot in the output pulse current, and the otherhas a wide pulse width generated at timing of occurrence of theundershoot. Thus, operation of increasing the overshoot and undershootand then effecting an improvement on each of the overshoot andundershoot is conducted. As a result, a further higher slew rate can beachieved.

[0159] According to the still another aspect of the invention, the firstN-type transistor connected at the first signal electrode thereof to theoutput terminal of an output pulse current functions as the constantcurrent source according to the bias voltage of the positive polarity.The second N-type transistor connected to the second signal electrode ofthe first N-type transistor and ground receives the output of the CMOSinverter that inverts the input pulse applied thereto and outputs theinverted pulse, switches the current of the constant current source, andthus generates the output pulse current. An overshoot and an undershootmay appear or may not appear on the output pulse current depending on aswitching speed of the second N-type transistor. Therefore, it becomespossible to prevent the overshoot and undershoot from appearing on theoutput pulse current, by adjusting the current quantities of the currentsource and the current mirror circuits that supply the current to theCMOS inverter and thereby setting the switching speed of the secondN-type transistor suitably.

[0160] According to the still another aspect of the invention, the firstand second N-type transistors each connected at the first signalelectrode thereof to the output terminal of an output pulse currentfunction respectively as the first and second constant current sourcesaccording to the bias voltage of the positive polarity. The third N-typetransistor connected to the second signal electrode of the first N-typetransistor and ground, switches the current of the first constantcurrent source in response to the input pulse of the positive polarityand thus generates the output pulse current. An overshoot and anundershoot appear on the output pulse current. Therefore, the fourthN-type transistor connected to the second signal electrode of the secondN-type transistor and the ground is made to conduct the switchingoperation in response to the correction pulse of the positive polarityprovided with the valley portion at timing of occurrence of an overshootin the output pulse current and the hill portion at timing of occurrenceof an undershoot in the output pulse current, and thus generate thecorrection pulse current. The correction pulse current is output to theoutput terminal together with the output terminal. As a result, thecorrection pulse current and the output pulse current are addedtogether. Thus, the output pulse current improved in overshoot andundershoot is output from the output terminal. Since the overshoot andundershoot can be thus improved without requiring any externalcomponent, a higher slew rate can be achieved.

[0161] Moreover, the first N-type transistor connected at the firstsignal electrode thereof to the output terminal of the output pulsecurrent functions as the first constant current source according to thefixed bias voltage of the positive polarity. The second N-typetransistor connected at the first signal electrode thereof to the outputterminal of the output pulse current functions as the second constantcurrent source according to the variable bias voltage of the positivepolarity. As a result, the correction pulse current can be adjustedsuitably. Therefore, appropriate improvement of the overshoot andundershoot can be effected.

[0162] According to the still another aspect of the invention, the firstN-type transistor connected at the first signal electrode thereof to theoutput terminal of the output pulse current functions as the firstconstant current source according to the bias voltage of the positivepolarity. The second N-type transistor connected to the second signalelectrode of the first N-type transistor and ground switches the currentof the first constant current source in response to the input pulse ofthe positive polarity and thus generates the output pulse current. Anovershoot and an undershoot appear on the output pulse current.Therefore, the third N-type transistor connected to the output terminaland the ground is made to conduct the switching operation in response tothe correction pulse of the positive polarity provided with the valleyportion at timing of occurrence of an overshoot in the output pulsecurrent and the hill portion at timing of occurrence of an undershoot inthe output pulse current, and thus generate the correction pulsecurrent. The correction pulse current is output to the output terminaltogether with the output terminal. As a result, the correction pulsecurrent and the output pulse current are added together. Thus, theoutput pulse current improved in overshoot and undershoot is output fromthe output terminal. Since the overshoot and undershoot can be thusimproved without requiring any external component, a higher slew ratecan be achieved.

[0163] Although the invention has been described with respect to aspecific embodiment for a complete and clear disclosure, the appendedclaims are not to be thus limited but are to be construed as embodyingall modifications and alternative constructions that may occur to oneskilled in the art which fairly fall within the basic teaching hereinset forth.

What is claimed is:
 1. A pulse current generation circuit comprising: afirst N-type transistor that is connected at a first signal electrodethereof to an output terminal of an output pulse current, and thatfunctions as a first constant current source according to a bias voltageof a positive polarity; a second N-type transistor that is connected toa second signal electrode of the first N-type transistor and ground, andthat switches a current of the first constant current source in responseto an input pulse of a positive polarity and thus generates the outputpulse current; a first P-type transistor that is connected at a firstsignal electrode thereof to the output terminal and that functions as asecond constant current source according to a bias voltage of a negativepolarity; a second P-type transistor that is connected to a secondsignal electrode of the first P-type transistor and a power supply, andthat switches a current of the second constant current source inresponse to a first correction pulse of a negative polarity appliedthereto at timing of occurrence of an overshoot in the output pulsecurrent and thus generates a first correction pulse current; a thirdN-type transistor that is connected at a first signal electrode thereofto the output terminal, and that functions as a third constant currentsource according to a bias voltage of a positive polarity; and a fourthN-type transistor that is connected to a second signal electrode of thethird N-type transistor and the ground, and that switches a current ofthe third constant current source in response to a second correctionpulse of a positive polarity applied thereto at timing of occurrence ofan undershoot in the output pulse current and thus generates a secondcorrection pulse current.
 2. The pulse current generation circuitaccording to claim 1, wherein each of the first P-type transistor andthe third N-type transistor has a variable bias voltage source.
 3. Thepulse current generation circuit according to claim 1, wherein the firstcorrection pulse includes two pulses of a negative polarity, one havinga wide pulse width generated at timing of occurrence of the overshoot inthe output pulse current, and the other having a narrow pulse widthgenerated at timing of occurrence of the undershoot, and the secondcorrection pulse includes two pulses of a positive polarity, one havinga narrow pulse width, generated at timing of occurrence of the overshootin the output pulse current, and the other having a wide pulse widthgenerated at timing of occurrence of the undershoot.
 4. A pulse currentgeneration circuit comprising: a first N-type transistor that isconnected at a first signal electrode thereof to an output terminal ofan output pulse current, and that functions as a first constant currentsource according to a bias voltage of a positive polarity; a secondN-type transistor that is connected to a second signal electrode of thefirst N-type transistor and ground, and that switches a current of thefirst constant current source in response to an input pulse of apositive polarity and thus generates the output pulse current; a firstP-type transistor that is connected at a first signal electrode thereofto the output terminal, and that functions as a second constant currentsource according to a bias voltage of a negative polarity; a secondP-type transistor that is connected to a second signal electrode of thefirst P-type transistor and a power supply, and that switches a currentof the second constant current source in response to a first correctionpulse of a negative polarity applied thereto at timing of occurrence ofan overshoot in the output pulse current and thus generates a firstcorrection pulse current; and a third N-type transistor that isconnected to the second signal electrode of the first N-type transistorand the ground, and that switches a current of the first constantcurrent source in response to a second correction pulse of a positivepolarity applied thereto at timing of occurrence of an undershoot in theoutput pulse current and thus generates a second correction pulsecurrent.
 5. A pulse current generation circuit comprising: a firstN-type transistor that is connected at a first signal electrode thereofto an output terminal of an output pulse current, and that functions asa first constant current source according to a bias voltage of apositive polarity; a second N-type transistor that is connected to asecond signal electrode of the first N-type transistor and ground, andthat switches a current of the first constant current source in responseto an input pulse of a positive polarity and thus generates the outputpulse current; a P-type transistor that is connected to a power supplyand the output terminal, and that conducts a switching operation inresponse to a first correction pulse of a negative polarity appliedthereto at timing of occurrence of an overshoot in the output pulsecurrent and thus generates a first correction pulse current; and a thirdN-type transistor that is connected to the output terminal and theground, and that conducts a switching operation in response to a secondcorrection pulse of a positive polarity applied thereto at timing ofoccurrence of an undershoot in the output pulse current and thusgenerates a second correction pulse current.
 6. The pulse currentgeneration circuit according to claim 5, wherein the first correctionpulse includes two pulses of a negative polarity, one having a widepulse width generated at timing of occurrence of the overshoot in theoutput pulse current, and the other having a narrow pulse widthgenerated at timing of occurrence of the undershoot, and the secondcorrection pulse includes two pulses of a positive polarity, one havinga narrow pulse width generated at timing of occurrence of the overshootin the output pulse current, and the other having a wide pulse widthgenerated at timing of occurrence of the undershoot.
 7. A pulse currentgeneration circuit comprising: a CMOS inverter that inverts an inputpulse applied thereto and outputs an inverted pulse; a current source; acurrent mirror circuit that supplies an output current of the currentsource to the CMOS inverter; a first N-type transistor that is connectedat a first signal electrode thereof to an output terminal of an outputpulse current, and that functions as a constant current source accordingto a bias voltage of a positive polarity; a second N-type transistorthat is connected to a second signal electrode of the first N-typetransistor and ground, and that switches a current of the constantcurrent source in response to an output of the CMOS inverter and thusgenerates the output pulse current.
 8. A pulse current generationcircuit comprising: first and second N-type transistors that are eachconnected at a first signal electrode thereof to an output terminal ofan output pulse current, and that function respectively as first andsecond constant current sources according to a bias voltage of apositive polarity; a third N-type transistor that is connected to asecond signal electrode of the first N-type transistor and ground, andthat switches a current of the first constant current source in responseto an input pulse of a positive polarity and thus generates the outputpulse current; and a fourth N-type transistor that is connected to asecond signal electrode of the second N-type transistor and the ground,and that conducts a switching operation in response to a correctionpulse of a positive polarity provided with a valley portion at timing ofoccurrence of an overshoot in the output pulse current and with a hillportion at timing of occurrence of an undershoot in the output pulsecurrent, and thus generates a correction pulse current.
 9. The pulsecurrent generation circuit according to claim 8, wherein the firstN-type transistor functions as the first constant current sourceaccording to a fixed bias voltage of a positive polarity, and the secondN-type transistor functions as the second constant current sourceaccording to a variable bias voltage of a positive polarity.
 10. A pulsecurrent generation circuit comprising: a first N-type transistor that isconnected at a first signal electrode thereof to an output terminal ofan output pulse current, and that functions as a first constant currentsource according to a bias voltage of a positive polarity; a secondN-type transistor that is connected to a second signal electrode of thefirst N-type transistor and ground, and that switches a current of thefirst constant current source in response to an input pulse of apositive polarity and thus generates the output pulse current; and athird N-type transistor that is connected to the output terminal and theground, and that conducts a switching operation in response to acorrection pulse of a positive polarity provided with a valley portionat timing of occurrence of an overshoot in the output pulse current andwith a hill portion at timing of occurrence of an undershoot in theoutput pulse current, and thus generates a correction pulse current.